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Test Vector Reordering Method for Low Power Testing: Test Vector Reordering Method for Minimizing Power Dissipation in VLSI Circuits using Functional Metrics

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Attributes

Authors
Paramasivam, K., Gunavathi, K.
Genre
Technology & Engineering
Label
LAP LAMBERT Academic Publishing
Content Languages
[object Object], [object Object], [object Object]
Number Of Items
1
Number Of Pages
76
Publication Date
2012-07-18
Publisher
LAP LAMBERT Academic Publishing
Studio
LAP LAMBERT Academic Publishing
Lang
en-US
Adult Product
No

Product Identifiers

AIDAlgopix unique identifier
AIDGGWT26001
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